Description
This memory module provide 32Kb of Static Ram & 32Kb of EEPROM. You can select – with jumpers – which one will occupy the 0-7FFF (LOW) & 8000-FFFF(HIGH) part of the 64Kb that are addressable by the CPU. You can see in the photo the green and pink jumpers on the top-left side. My design uses 0-7FFF for ROM(pink) and 8000-FFFF for RAM(green)
Also it is possible to make the EEPROM writable by setting a Jumper on the board and then issuing an OUT command. This controls the flip flop that allows(HIGH) or not (LOW) the WR signal to reach the the EEPROM. (NOT TESTED YET).
J-SETROMWR should be connected to one of the spares or the extensions and the same should be done on the DEVICE MODULE that controls the out signals. In my design i use Spare 5 the last pin (the photo is wrong). Spare 5 is connected to OUT (8) on the DEVICE MODULE. This port is used for controlling the various FLIP-FLOPS so it uses just one bit to control the EEPROM FF. I am using D0 so J_DATABIT_SEL is connected to D0 (Picture is correct).
This design is used so far with slow RAM and ROM(150ns) so i managed to run the cpu up to 10MHz without problems. For reaching 20MHz i designed two PCBs with fast sram and eeproms but these have not been tested yet.
Schematics
PCB
