Newbrain Expansion Port

Pin	Signal Name	Description / Notes	EIM
1	GND	Ground	50E
2	Z80 CLOCK 4MHz	System Clock (Directly for CPU/Bus)	49E
3	A14	Address Bus Bit 14	48E
4	A13	Address Bus Bit 13	47E
5	D5	Data Bus Bit 5	46E
6	RMSL	RAM Select (connect to ground to switch 16k rams)	45E
7	D4	Data Bus Bit 4	44E
8	D3	Data Bus Bit 3	43E
9	D6	Data Bus Bit 6	42E
10	D7	Data Bus Bit 7	41E
11	A11	Address Bus Bit 11	40E
12	A10	Address Bus Bit 10	39E
13	A8	Address Bus Bit 8	38E
14	A9	Address Bus Bit 9	37E
15	A12	Address Bus Bit 12	36E
16	A7	Address Bus Bit 7	35E
17	A3	Address Bus Bit 3	34E
18	A2	Address Bus Bit 2	33E
19	A1	Address Bus Bit 1	32E
20	A0	Address Bus Bit 0	31E
21	D0	Data Bus Bit 0	30E
22	D1	Data Bus Bit 1	29E
23	FCTR	Functional Counter / Clock?	28E
24	D2	Data Bus Bit 2	27E
25	A5	Address Bus Bit 5	26E
26	A6	Address Bus Bit 6	25E
27	RAMENB	RAM Enable (Internal logic toggle)	24E
28	EXRM2	Expansion RAM Page Bit 2 (Output to NB)	23E
29	EXRM1	Expansion RAM Page Bit 1 (Output to NB)	22E
30	EXRM0	Expansion RAM Page Bit 0 (Output to NB)	21E
31	nROMOV	ROM Override	20E
32	nBUSRQ	Bus Request	19E
33	nM1	Machine Cycle 1 (Opcode Fetch)	18E
34	nRST	Reset Signal	17E
35	RFRSH	DRAM Refresh (Safe to ignore for SRAM)	16E
36	nWAIT	CPU Wait State	15E
37	A4	Address Bus Bit 4	14E
38	nBUSACK	Bus Acknowledge (CPU has released bus)	13E
39	A15	Address Bus Bit 15	12E
40	nWR	Write Enable	11E
41	nINT	Interrupt Request	10E
42	nRD	Read Enable	9E
43	nNMI	Non-Maskable Interrupt	8E
44	nHALT	CPU Halt State	7E
45	nMREQ	Memory Request	6E
46	nIOREQ	I/O Request	5E
47	PRTOV	Port 0xFF Override / Select	4E
48	RAMINH	RAM Inhibit	3E
49	+5V	System Power	2E
50	BUSRQ	Bus Request (TV)	1E