| 1 | GND | Ground | 50E |
| 2 | Z80 CLOCK 4MHz | System Clock (Directly for CPU/Bus) | 49E |
| 3 | A14 | Address Bus Bit 14 | 48E |
| 4 | A13 | Address Bus Bit 13 | 47E |
| 5 | D5 | Data Bus Bit 5 | 46E |
| 6 | RMSL | RAM Select (connect to ground to switch 16k rams) | 45E |
| 7 | D4 | Data Bus Bit 4 | 44E |
| 8 | D3 | Data Bus Bit 3 | 43E |
| 9 | D6 | Data Bus Bit 6 | 42E |
| 10 | D7 | Data Bus Bit 7 | 41E |
| 11 | A11 | Address Bus Bit 11 | 40E |
| 12 | A10 | Address Bus Bit 10 | 39E |
| 13 | A8 | Address Bus Bit 8 | 38E |
| 14 | A9 | Address Bus Bit 9 | 37E |
| 15 | A12 | Address Bus Bit 12 | 36E |
| 16 | A7 | Address Bus Bit 7 | 35E |
| 17 | A3 | Address Bus Bit 3 | 34E |
| 18 | A2 | Address Bus Bit 2 | 33E |
| 19 | A1 | Address Bus Bit 1 | 32E |
| 20 | A0 | Address Bus Bit 0 | 31E |
| 21 | D0 | Data Bus Bit 0 | 30E |
| 22 | D1 | Data Bus Bit 1 | 29E |
| 23 | FCTR | Functional Counter / Clock? | 28E |
| 24 | D2 | Data Bus Bit 2 | 27E |
| 25 | A5 | Address Bus Bit 5 | 26E |
| 26 | A6 | Address Bus Bit 6 | 25E |
| 27 | RAMENB | RAM Enable (Internal logic toggle) | 24E |
| 28 | EXRM2 | Expansion RAM Page Bit 2 (Output to NB) | 23E |
| 29 | EXRM1 | Expansion RAM Page Bit 1 (Output to NB) | 22E |
| 30 | EXRM0 | Expansion RAM Page Bit 0 (Output to NB) | 21E |
| 31 | nROMOV | ROM Override | 20E |
| 32 | nBUSRQ | Bus Request | 19E |
| 33 | nM1 | Machine Cycle 1 (Opcode Fetch) | 18E |
| 34 | nRST | Reset Signal | 17E |
| 35 | RFRSH | DRAM Refresh (Safe to ignore for SRAM) | 16E |
| 36 | nWAIT | CPU Wait State | 15E |
| 37 | A4 | Address Bus Bit 4 | 14E |
| 38 | nBUSACK | Bus Acknowledge (CPU has released bus) | 13E |
| 39 | A15 | Address Bus Bit 15 | 12E |
| 40 | nWR | Write Enable | 11E |
| 41 | nINT | Interrupt Request | 10E |
| 42 | nRD | Read Enable | 9E |
| 43 | nNMI | Non-Maskable Interrupt | 8E |
| 44 | nHALT | CPU Halt State | 7E |
| 45 | nMREQ | Memory Request | 6E |
| 46 | nIOREQ | I/O Request | 5E |
| 47 | PRTOV | Port 0xFF Override / Select | 4E |
| 48 | RAMINH | RAM Inhibit | 3E |
| 49 | +5V | System Power | 2E |
| 50 | BUSRQ | Bus Request (TV) | 1E |
A quick observation on the connector image in your Expansion Port post.
The two green circles are clear: pin 1 at the bottom-left, and pin 6 on the top row, third position. Together they fix the numbering scheme: odd pins (1, 3, … 49) along the bottom row and even pins (2, 4, … 50) along the top, running left to right as viewed from the rear with the keying notch at the bottom.
The two red circles are harder to read: their callout arrows point in from outside the frame, so their labels seem to have been cropped out of the published image. As placed, one sits on the bottom row around the 22nd–23rd position and the other on the top row at the far right. If they’re meant to mark pins 46 and 49, that doesn’t fit the scheme the green circles establish – pin 46 is even and would be on the top row, pin 49 is odd and would be on the bottom row, and the top-rightmost pin would be 50. Could you clarify which pins the red circles mark, or re-upload the image at full resolution with the labels included, please?
Also, out of interest: how did you establish the pin-1 position — continuity to ground, tracing on the main board, or another way? I’m doing some work against this connector and would like to know how firmly the orientation is established. Many thanks
The two green circles are correct and if you jumper them you switch banks in ram low 16k becomes high and vice versa. The red ones was pointed to do that from another site and when i tried it it didnt work so i traced the problem and it was numbered incorrectly. The photo is from another post that i did to point out that issue.
One other point on the signal table. Your pin 23 entry – FCTR, “Functional Counter / Clock?” – caught my eye. The Grundy Software Technical Manual Appendix E lists pin 23 as unused, but with an interesting note: early machines do carry a signal on it, and Appendix E advises a 10 kΩ pull-up to 5 V and warns against driving the pin. The Expansion Board documentation agrees. Do you know where the FCTR identification came from: was it traced on a physical NewBrain, or from another source? If it names the signal the early machines carried, that would be a real find, since the Grundy material never identifies it.
Two smaller naming points, mainly for anyone cross-referencing against the Grundy documents: pin 48 appears there as RAMINB (“logic one inhibits Z80A request to internal RAM”) rather than RAMINH – I think RAMINH may be MAME’s name for it – and PRTOV on pin 47 is described more generally as inhibiting the machine’s internal I/O port decode, rather than as a port 0xFF select. Appendix F’s port 255 paging/status-register mechanism appears to be a separate thing, so I’d also be interested to know whether your 0xFF description comes from tracing the hardware or another source. Many thanks.
The comments are from Gemini when i was trying to replace the drams with a sram so some of them could be just guessing. FCTR is the name on the schematics and so is the prtov. Now fctr i do not know what it does but prtov is port override probably. Raminh is also how the schematics has it and it is probably correct.
Thanks, Chris. That clears it up nicely, and the provenance of the annotations is particularly helpful.
For anyone else using the photograph as a connector reference, my understanding from your explanation is:
* the two green circles are the correct positions. They are pins 1 (GND) and 6 (RMSL), so linking them grounds RMSL and swaps the low/high 16K RAM banks;
* the red circles are deliberately showing the incorrect positions from another published source which you subsequently found did not work and traced as a numbering error. So they shouldn’t be read as additional pin-number callouts on this image;
* the explanatory descriptions in the table were partly generated with Gemini during your SRAM-replacement work, so those descriptions shouldn’t necessarily be treated as source documentation;
* however, the signal names FCTR, PRTOV and RAMINH came from the schematics rather than from Gemini.
The FCTR point is especially interesting. The Grundy Software Technical Manual Appendix E leaves pin 23 unnamed/unused for expansion purposes, but notes that early machines carry a signal on it and advises a 10K pull-up to +5V and that the pin should not be driven. I’ve since also found a NewBrain On-Line magazine description which says pin 23 goes into the video circuitry; pulling it low shifts the picture two positions to the left, and noise on it can cause picture jitter; again recommending a 10K pull-up. So FCTR may well be the actual schematic name of that otherwise rather mysterious early-machine signal.
If you happen to know which schematic or NewBrain board revision shows the name FCTR, that would be very useful to pin down.
Likewise, for anyone cross-referencing sources, there seems simply to be some nomenclature variation around pin 48: the Grundy Software Technical Manual uses RAMINB, whereas the schematic material you have uses RAMINH; both describe the same RAM-inhibit function.
Many thanks again for taking the time to check this and explain how the photograph came about – it makes the page much more useful as a reference.
You can check on the forum here https://newbrainemu.eu/forums/topic/newbrain-ram-banks-switch-2/
I only have seen one schematic if you search here you can find it, the pdf contains all schematics for all known grundy hardware
Thanks Chris, found it. You were quite right: the Grundy main-board schematic does explicitly label the expansion pin 23 signal FCTR, and I can also see RAMINH and PRTOV there.
That clears up the apparent discrepancy nicely. Appendix E of the Software Technical Manual doesn’t name FCTR, but its warning about pin 23 now makes sense alongside the schematic: it is an internal signal brought out on early machines, rather than a signal intended for use by expansion hardware.
The NewBrain On-Line material adds the behavioural piece: pin 23 goes into the video circuitry; pulling it low shifts the picture two positions and interference can cause picture jitter, hence the recommendation for a 10K pull-up to +5V.
So for anyone coming across this later: FCTR is a genuine Grundy schematic signal name; “Functional Counter / Clock?” was only the tentative description and shouldn’t be taken as the meaning of the acronym. I haven’t yet found a Grundy document that actually expands FCTR.
Likewise, RAMINH is indeed the schematic nomenclature, while the Software Technical Manual uses RAMINB for the same RAM-inhibit function.
Many thanks for pointing me back to the schematic set – that resolves it.